It is possibly closer to say that I was aiming for the idea that the majority of the designer’s functional intent is captured in the fabric and not in the available hardened IP.” When FPGA vendors started cramming Ethernet ports, DSP slices, large SRAM blocks, and finally entire microprocessor subsystems into their parts, they ceased being ‘pure.’ However, the loss of purity came with a massive increase in utility.” The original Xilinx XC2064 was a ‘pure’ FPGA with nothing more on chip than programmable logic and interconnect. “Tim, ‘pure’ FPGAs left the building two decades ago. Well, if Tim was going to cite one of my EEJournal articles on LinkedIn, I felt that I’d better reply, so I wrote back: See Steve Leibson’s EE Journal article: Why does Xilinx say That its New 7nm Versal ‘ACAP’ isn’t an FPGA?“ “The warning shot, that FPGAs were on the way out, was delivered three years ago by Xilinx CEO Victor Peng. “It seems like the golden age of the pure FPGA is disappearing to me. It all started with a post from one of my LinkedIn connections, Tim Davis:
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